1Department of Electronics and Communication Engineering, KLE Dr. M.S. Sheshgiri College of Engineering and Technology, Belagavi,Karnataka, India
2Department of Electronics and Communication Engineering, KLE Dr. M.S. Sheshgiri College of Engineering and Technology, Belagavi ,Karnataka,India
3Department of Electronics & Communication Engineering, Hirasugar Institute of Technology, Nidasoshi,Karnataka,India
Corresponding author email: vidya.mallaraddi@gmail.com
Article Publishing History
Received: 12/10/2020
Accepted After Revision: 31/12/2020
Scaling down of transistors will directly affects the decreasing in threshold voltage. Impact of decreasing threshold voltage is increasing in leakage current. In this paper many power gating circuits are discussed for their advantages and disadvantages, based on this literature survey a novel low power state retention technique is proposed in this paper. The proposed technique with its novel architecture reduces the leakage power (static power) and dynamic power dissipations. It also gives the state retained output. Performance of the proposed circuit is evaluated on some basic circuits in terms of their total and dynamic power dissipations. Extensive SPICE simulations were carried out and the results are compared with some existing techniques. Simulated results shows that proposed technique gives the efficient power minimization and state retained standby mode output.
Feedback, Hpg, Low Power, Mtmos, On Current