Multipliers are the backbone of high-performance computing systems such as Microprocessors and Digital signal processors. Multipliers require more hardware resources and processing time, hence they are the slowest elements in the system. Multipliers are mainly used in today’s high-end Digital Signal Processors and they occupy a larger chip area because of their inherent internal circuit complexity. Present-day co-processors are designed to support different size computations to achieve high performance. Researchers have worked on signed and complex number multipliers used in co-processors of 64 bit and below. There is a scope for designing a higher bit complex number multiplier to achieve higher performance. In this context, we proposed to design of 128-bit complex number multiplier of various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier using ModelSim SE 6.4 and Xilinx Vivado.

In this work, various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier for 8-bit, 16- bit, 32-bit, 64-bit and 128-bit designed using Verilog for complex number multiplication. Nikhilam is one of the sutras of Vedic mathematics which is chosen for the implementation of complex number multiplier for area reduction. Synthesis reports are generated using the Xilinx Vivado tool for speed and power comparison. From the comparison, we have observed that Booth, Modified Booth, Urdhva, and Nikhilam occupy an area of 324.32%, 292.79%, 56.36%, and 46.70% respectively for 128-bit implementations. Among all the implemented methods, the Nikhilam method for complex number multiplier occupies very less area i.e. only 46.70% on-chip area.